AD9914SLASHPCBZ datasheet(40/45 Pages) AD

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AD9914

Data Sheet

Rev. F | Page 40 of 45

Bits

Mnemonic

Description

External OSK enable

0 = manual OSK enabled (default).

1 = automatic OSK enabled.

Ineffective unless CFR1[8] = 1.

OSK enable

0 = OSK disabled (default).

1 = OSK enabled. To engage any digital amplitude adjust using DRG, profile, or direct mode

via the 32-bit parallel port, or OSK pin, this bit must be set.

Digital power-down

This bit is effective without the need for an input/output update.

0 = clock signals to the digital core are active (default).

1 = clock signals to the digital core are disabled.

DAC power-down

0 = DAC clock signals and bias circuits are active (default).

1 = DAC clock signals and bias circuits are disabled.

REFCLK input power-down

This bit is effective without the need for an input/output update.

0 = REFCLK input circuits and PLL are active (default).

1 = REFCLK input circuits and PLL are disabled.

Open

Open.

External power-down control

0 = assertion of the EXT_PWR_DWN pin affects power-down.

1 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down.

Open

Open.

SDIO input only

0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming

mode (default).

1 = configures the serial data input/output pin (SDIO) as an input only pin; 3-wire serial

programming mode.

LSB first mode

0 = configures the serial input/output port for MSB-first format (default).

1 = configures the serial input/output port for LSB-first format.

Control Function Register 2 (CFR2)—Address 0x01

Table 16. Bit Descriptions for CFR2

Bit(s)

Mnemonic

Description

[31:24]

Open

Open.

Profile mode enable

0 = disables profile mode functionality (default).

1 = enables profile mode functionality. Profile pins select the desired profile.

Parallel data port enable

See the Parallel Data Port Modulation Mode section for more details.

0 = disables parallel data port modulation functionality (default).

1 = enables parallel data port modulation functionality.

[21:20]

Digital ramp destination

See Table 9 for details. Default is 00. See the Digital Ramp Generator (DRG) section for more details.

Digital ramp enable

0 = disables digital ramp generator functionality (default).

1 = enables digital ramp generator functionality.

Digital ramp no-dwell high

See the Digital Ramp Generator (DRG) section for details.

0 = disables no-dwell high functionality (default).

1 = enables no-dwell high functionality.

Digital ramp no-dwell low

See the Digital Ramp Generator (DRG) section for details.

0 = disables no-dwell low functionality (default).

1 = enables no-dwell low functionality.

Programmable modulus enable

0 = disables programmable modulus.

1 = enables programmable modulus.

Matched latency enable

0 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at

the output in the order listed in Table 2 under data latency (pipe line delay)(default).

1 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at

the output simultaneously.

Frequency jump enable

0 = disables frequency jump.

1 = enables frequency jump mode. Must have the digital generator DRG enabled for this feature.

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