AD9914SLASHPCBZ datasheet(19/45 Pages) AD

19 / 45 page

Data Sheet

AD9914

Rev. F | Page 19 of 45

FUNCTIONAL BLOCK DETAIL

DDS CORE

The direct digital synthesizer (DDS) block generates a reference

signal (sine or cosine based on Register 0x00, Bit 16, the enable

sine output bit). The parameters of the reference signal (frequency,

phase, and amplitude) are applied to the DDS at the frequency,

phase offset, and amplitude control inputs, as shown in Figure 30.

The output frequency (fOUT) of the AD9914 is controlled by the

frequency tuning word (FTW) at the frequency control input to

the DDS. The relationship among fOUT, FTW, and fSYSCLK is given by

SYSCLK

OUT

FTW

(1)

where FTW is a 32-bit integer ranging in value from 0 to

2,147,483,647 (231 − 1), which represents the lower half of the

full 32-bit range. This range constitutes frequencies from dc to

Nyquist (that is, ½ fSYSCLK).

The FTW required to generate a desired value of fOUT is found

by solving Equation 1 for FTW, as given in Equation 2.

SYSCLK

OUT

FTW

round

(2)

where the round(x) function rounds the argument (the value of

x) to the nearest integer. This is required because the FTW is

constrained to be an integer value. For example, for fOUT =

41 MHz and fSYSCLK = 122.88 MHz, FTW = 1,433,053,867

(0x556AAAAB).

Programming an FTW greater than 231 produces an aliased

image that appears at a frequency given by

SYSCLK

OUT

FTW

for FTW ≥ 231

The relative phase of the DDS signal can be digitally controlled

by means of a 16-bit phase offset word (POW). The phase offset

is applied prior to the angle to amplitude conversion block internal

to the DDS core. The relative phase offset (Δθ) is given by

360

POW

where the upper quantity is for the phase offset expressed as

radian units and the lower quantity as degrees.

To find the POW value necessary to develop an arbitrary Δθ,

solve the preceding equation for POW and round the result (in

a manner similar to that described previously for finding an

arbitrary FTW).

The relative amplitude of the DDS signal can be digitally scaled

(relative to full scale) by means of a 12-bit amplitude scale factor

(ASF). The amplitude scale value is applied at the output of the

angle to amplitude conversion block internal to the DDS core.

The amplitude scale is given by

log

ASF

Scale

Amplitude

(3)

where the upper quantity is amplitude expressed as a fraction of

full scale and the lower quantity is expressed in decibels relative

to full scale.

To find the ASF value necessary for a particular scale factor, solve

Equation 3 for ASF and round the result (in a manner similar to

that described previously for finding an arbitrary FTW).

When the AD9914 is programmed to modulate any of the DDS

signal control parameters, the maximum modulation sample

rate is 1/24 fSYSCLK. This means that the modulation signal exhibits

images at multiples of 1/24 fSYSCLK. The impact of these images

must be considered when using the device as a modulator.

DDS_CLK

FREQUENCY

CONTROL

ANGLE-TO-

AMPLITUDE

CONVERSION

(SINE OR

COSINE)

PHASE

OFFSET

CONTROL

TO DAC

(MSBs)

D Q

ACCUMULATOR

RESET

MSB ALIGNED

AMPLITUDE

CONTROL

DDS SIGNAL CONTROL PARAMETERS

32-BIT

ACCUMULATOR

Figure 30. DDS Block Diagram

AD9914/PCBZ Scheda tecnica(PDF) 19 Page - Analog Devices

AD9914/PCBZ Scheda tecnica(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Scheda tecnica Scarica

Link URL