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AD9914/PCBZ Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD9914/PCBZ Scheda tecnica(HTML) 11 Page - Analog Devices |
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11 / 45 page ![]() Data Sheet AD9914 Rev. F | Page 11 of 45 Pin No. Mnemonic I/O1 Description 67 EXT_PWR_DWN I External Power-Down. Digital input (active high). A high level on this pin initiates the currently programmed power-down mode. 82 SYNC_CLK O Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE, PS[2:0], and the parallel data port (D0 to D31), must be set up on the rising edge of this signal. 85 MASTER_RESET I Master Reset. Digital input (active high). Clears all memory elements and sets registers to default values. 86 I/O_UPDATE I Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the input/output buffers to the corresponding internal registers. EPAD Exposed Pad. The EPAD must be soldered to ground. 1 I = input, O = output. |
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