AD9914SLASHPCBZ datasheet(22/45 Pages) AD

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AD9914

Data Sheet

Rev. F | Page 22 of 45

PLL Charge Pump/Total Feedback Divider

The charge pump current (ICP) value is automatically chosen via

the VCO calibration process and N value (N = 10 to 255) stored

in Feedback Divider N[7:0] in the CFR3 register (0x02[15:8]). N

values below 10 must be avoided.

Note that the total PLL multiplication value for the PLL is always

2N due to the fixed divide by 2 element in the feedback path.

This is shown in Figure 34. This fixed divide by 2 element forces

only even PLL multiplication.

To manually override the charge pump current value, the manual

ICP selection bit in CFR3 (0x02[6]) must be set to Logic 1. This

provides the user with additional flexibility to optimize the PLL

performance. Table 7 lists the bit settings vs. the nominal charge

pump current.

Table 7. PLL Charge Pump Current

ICP Bits (CFR3[5:3])

Charge Pump Current, ICP (μA)

000

125

001

250

010

375

011

500 (default)

100

625

101

750

110

875

111

1000

Table 8. N Divider vs. Charge Pump Current

N Divider Range

Recommended Charge Pump

Current, ICP (μA)

10 to 15

125

16 to 23

250

24 to 35

375

36 to 43

500

44 to 55

625

56 to 63

750

64 to 79

875

80 to 100

1000

PLL Loop Filter Components

The loop filter is mostly internal to the device, as shown in

Figure 34. The recommended external capacitor value is 560 pF.

Because CP and RPZ are integrated, it is not recommended to

adjust the loop bandwidth via the external capacitor value. The

better option is to adjust the charge pump current even though

it is a coarse adjustment.

For example, suppose the PLL is manually programmed such

that ICP = 375 μA, KV = 60 MHz/V, and N = 25. This produces a

loop bandwidth of approximately 250 kHz.

PFD

LOOP_FILTER

VCO

÷N

÷2

PLL OUT

PLL IN

REFCLK PLL

RPZ (3.5k )

CZ = 560pF (RECOMMENDED)

REF

0.47µF

50pF

Figure 34. REF CLK PLL External Loop Filter

PLL LOCK INDICATION

When the PLL is in use, the PLL lock bit (0x1B[24])provides an

active high indication that the PLL has locked to the REF CLK

input signal.

OUTPUT SHIFT KEYING (OSK)

The OSK function (see Figure 35) allows the user to control the

output signal amplitude of the DDS. The amplitude data generated

by the OSK block has priority over any other functional block

that is programmed to deliver amplitude data to the DDS.

Therefore, the OSK data source, when enabled, overrides all

other amplitude data sources.

The operation of the OSK function is governed by two CFR1

(0x00[9]), the external OSK pin, the profile pins, and the 12 bits

of amplitude scale factor found in one of eight profile registers.

The profile pins select the profile register containing the desired

amplitude scale factor.

The primary control for the OSK block is the OSK enable bit

(0x00[8]). When the OSK function is disabled, the OSK input

controls and OSK pin are ignored.

The OSK pin functionality depends on the state of the external

OSK enable bit and the OSK enable bit. When both bits are set

to Logic 1 and the OSK pin is Logic 0, the output amplitude is

forced to 0; otherwise, if the OSK pin is Logic 1, the output

amplitude is set by the amplitude scale factor value in one of

eight profile registers depending on the profile pin selection.

OSK ENABLE

EXTERNAL

OSK ENABLE

OSK

DDS CLOCK

PS0 PS1 PS2

TO DDS

AMPLITUDE

CONTROL

PARAMETER

OSK

CONTROLLER

AMPLITUDE SCALE

FACTOR (1 OF 8

SELECTED PROFILE

REGISTERS [27:16])

Figure 35. OSK Block Diagram

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