MCP47FXB2XT-EST datasheet(116/124 Pages) MICROCHIP

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MCP47FXBX4/8

DS20006368A-page 116

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C.4

Full-Scale Error (EFS)

The Full-Scale error (see Figure C-3) is the error on

the VOUT pin relative to the expected VOUT voltage

(theoretical) for the maximum device DAC register

code (code FFFh for 12-bit, code 3FFh for 10-bit, and

code FFh for 8-bit), see Equation C-2. The error

depends on the resistive load on the VOUT pin (and

where that load is tied to, such as VSS or VDD). For

loads (to VSS) greater than specified, the Full-Scale

error will be greater.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

EQUATION C-2:

FULL-SCALE ERROR

C.5

Zero-Scale Error (EZS)

The Zero-Scale error (see Figure C-2) is the difference

between the ideal and the measured VOUT voltage with

the DAC register code equal to 000h (Equation C-3).

The error depends on the resistive load on the VOUT pin

(and where that load is tied to, such as VSS or VDD). For

loads (to VDD) greater than specified, the Zero-Scale

error will be greater.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

EQUATION C-3:

ZERO SCALE ERROR

C.6

Total Unadjusted Error (ET)

The Total Unadjusted error (ET) is the difference

between the ideal and measured VOUT voltage. Typi-

cally, calibration of the output voltage is implemented

to improve system’s performance.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

Equation C-4 shows the Total Unadjusted error

calculation:

EQUATION C-4:

TOTAL UNADJUSTED

ERROR CALCULATION

Where:

EFS is expressed in LSb.

VOUT(@FS) is the VOUT voltage when the DAC

VIDEAL(@FS) is the ideal output voltage when the

DAC register code is at full scale.

VLSb(IDEAL) is the theoretical voltage step size.

EFS

VOUT(@FS) VIDEAL(@FS)

–

VLSb(IDEAL)

---------------------------------------------------------------------------

Where:

EFS is expressed in LSb.

VOUT(@ZS) is the VOUT voltage when the DAC

VLSb(IDEAL) is the theoretical voltage step size.

EZS

VOUT(@ZS)

VLSb(IDEAL)

----------------------------------

Where:

ET is expressed in LSb.

VOUT_Actual(@Code) = The measured DAC

output voltage at the

specified code

VOUT_Ideal(@Code) = The calculated DAC

output voltage at the

specified code

(code × VLSb(Ideal))

VLSb(Ideal) =VREF/# Steps

12-bit = VREF/4096

10-bit = VREF/1024

8-bit = VREF/256

VOUT_Actual(@Code) VOUT_Ideal(@Code)

–



VLSb(Ideal)

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