MCP47FXB2XT-EST datasheet(119/124 Pages) MICROCHIP

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DS20006368A-page 119

MCP47FXBX4/8

C.13

Settling Time

The settling time is the time delay required for the VOUT

voltage to settle into its new output value. This time is

measured from the start of code transition to when the

VOUT voltage is within the specified accuracy.

For the MCP47FXBX4/8, the settling time is a mea-

surement of the time delay until the VOUT voltage

reaches within 0.5 LSb of its final value, when the vol-

atile DAC register changes from 1/4 to 3/4 of the FSR

(12-bit device: 400h to C00h).

C.14

Major Code Transition Glitch

Major code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes the state. It is normally spec-

ified as the area of the glitch in nV-Sec and is measured

when the digital code is changed by 1 LSb at the major

carry transition (Example: 011...111 to 100...

000, or 100... 000 to 011 ... 111).

C.15

Digital Feed-through

The digital feed-through is the glitch that appears at the

analog output caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec and is measured with a full-scale change

(Example: all ‘0’s to all ‘1’s and vice versa) on the digital

input pins. The digital feed-through is measured when

the DAC is not written to the output register.

C.16

-3 dB Bandwidth

This is the frequency of the signal at the VREF pin that

causes the voltage at the VOUT pin to fall -3 dB from a

static value on the VREF pin. The output decreases due

to the RC characteristics of the resistor ladder and the

characteristics of the output buffer.

C.17

Power-Supply Sensitivity (PSS)

PSS indicates how the output of the DAC is affected by

changes in the supply voltage. PSS is the ratio of the

change in VOUT to a change in VDD for mid-scale output

of the DAC. The VOUT is measured while the VDD is

varied from 5.5V to 2.7V as a step (VREF voltage held

constant), and expressed in %/%, which is the %

change of the DAC output voltage with respect to the %

change of the VDD voltage.

EQUATION C-8:

PSS CALCULATION

C.18

Power-Supply Rejection Ratio

(PSRR)

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in VOUT to a change in VDD for full-scale

output of the DAC. The VOUT is measured while the

VDD is varied ±10% (VREF voltage held constant) and

expressed in dB or µV/V.

C.19

VOUT Temperature Coefficient

The VOUT temperature coefficient quantifies the error in

the resistor ladder’s resistance ratio (DAC register

code value) and output buffer due to temperature drift.

C.20

Absolute Temperature Coefficient

The absolute temperature coefficient quantifies the

error in the end-to-end output voltage (nominal output

voltage VOUT) due to temperature drift. For a DAC, this

error is typically not an issue due to the ratiometric

aspect of the output.

C.21

Noise Spectral Density

The noise spectral density is a measurement of the

device’s internally generated random noise and is

characterized as a spectral density (voltage per √Hz).

It is measured by loading the DAC to the mid-scale

value and measuring the noise at the VOUT pin. It is

measured in nV/√Hz.

Where:

PSS is expressed in % / %.

VOUT(@5.5V) = The measured DAC output

voltage with VDD = 5.5V

VOUT(@2.7V) = The measured DAC output

voltage with VDD = 2.7V

PSS

VOUT(@5.5V) VOUT(@2.7V)

–

 V

OUT(@5.5V)



5.5V 2.7V

–

 5.5V





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