ADSP-SC596 datasheet(102/134 Pages) AD

102 / 134 page

Rev. PrD

Page 102 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

10/100/1000 EMAC Timing (ETH0 Only)

Table 69 and Figure 39 describe the RGMII EMAC timing.

Table 69. 10/100/1000 EMAC Timing—RGMII Receive and Transmit Signals1

1 This specification is supported by ETH0 only (10/100/1000 EMAC controller).

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSETUPR

Data to Clock Input Setup at Receiver

tHOLDR

Data to Clock Input Hold at Receiver

tGREFCLKF

RGMII Receive Clock Period

tGREFCLKW

RGMII Receive Clock Pulse Width

Switching Characteristics

tSKEWT

Data to Clock Output Skew at Transmitter

–0.5

+0.5

tCYC

Clock Cycle Duration

7.2

8.8

tDUTY_G

Duty Cycle for RGMII Minimum

tGREFCLKF × 45%

tGREFCLKF × 55%

Figure 39. Gigabit EMAC Controller Timing—RGMII

HOLDR

ETH_TXCLK

(AT TRANSMITTER)

ETH_TXD3–0

ETH_TXCTL_TXEN

SKEWT

DUTY_G

CYC

GREFCLKF

GREFCLKW

ETH_RXCLK_REFCLK

(AT RECEIVER)

ETH_RXD3–0

ETH_RXCTL_CRS

SETUPR

GREFCLKW

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