ADSP-SC596 datasheet(106/134 Pages) AD

106 / 134 page

Rev. PrD

Page 106 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Table 71. Enhanced Parallel Peripheral Interface (EPPI)—External Clock

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tPCLKW

EPPI_CLK Width1

0.5 × tPCLKEXT – 0.5

tPCLK

EPPI_CLK Period1

tPCLKEXT – 1

tSFSPE

External FS Setup Before EPPI_CLK

tHFSPE

External FS Hold After EPPI_CLK

3.7

tSDRPE

Receive Data Setup Before EPPI_CLK

tHDRPE

Receive Data Hold After EPPI_CLK

3.7

Switching Characteristics

tDFSPE

Internal FS Delay After EPPI_CLK

15.3

tHOFSPE

Internal FS Hold After EPPI_CLK

2.4

tDDTPE

Transmit Data Delay After EPPI_CLK

15.3

tHDTPE

Transmit Data Hold After EPPI_CLK

2.4

1 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external

EPPI_CLK ideal maximum frequency, see the fPCLKEXT specification in Table 22.

Figure 45. EPPI External Clock GP Receive Mode with Internal Frame Sync Timing

Figure 46. EPPI External Clock GP Transmit Mode with Internal Frame Sync Timing

tHDRPE

tSDRPE

tHOFSPE

FRAME SYNC

DRIVEN

DATA

SAMPLED

tDFSPE

tPCLK

tPCLKW

EPPI_D00-23

EPPI_FS1/2

EPPI_CLK

POLC[1:0] = 10

POLC[1:0] = 01

tHOFSPE

FRAME SYNC

DRIVEN

DATA

DRIVEN

tDFSPE

tDDTPE

tHDTPE

tPCLK

tPCLKW

DATA

DRIVEN

EPPI_D00-23

EPPI_FS1/2

EPPI_CLK

POLC[1:0] = 11

POLC[1:0] = 00

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