STR750F datasheet(61/73 Pages) STMICROELECTRONICS

61 / 73 page

STR750F

Electrical parameters

61/71

3.3.10

Communication interface characteristics

I2C - Inter IC control interface

Subject to general operating conditions for VDD_IO, fPCLK, and TA unless otherwise specified.

The ST7 I2C interface meets the requirements of the Standard I2C communication protocol

described in the following table with the restriction mentioned below:

Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-

Drain: when configured as open-drain, the PMOS connected between the I/O pin and

VDD_IO is disabled, but it is still present. Also, there is a protection diode between the

I/O pin and VDD_IO. Consequently, when using this I2C in a multi-master network, it is

not possible to power off the STR7x while some another I2C master node remains

powered on: otherwise, the STR7x will be powered by the protection diode.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Table 37.

SDA and SCL characteristics

Symbol

Parameter

Standard mode

I2C

Fast mode I2C(1)

fPCLK, must be at least 8 MHz to achieve max fast I

2C speed (400 kHz).

Unit

Min(2)

Data based on standard I2C protocol requirement, not tested in production.

Max(2)

Min(2)

Max(2)

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

0(3)

The maximum hold time of the START condition has only to be met if the interface does not stretch the low

period of SCL signal.

0(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

900(3)

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

20+0.1Cb

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

20+0.1Cb

300

th(STA)

START condition hold time

4.0

0.6

µs

tsu(STA)

Repeated START condition setup time

4.7

0.6

tsu(STO)

STOP condition setup time

4.0

0.6

µs

tw(STO:STA) STOP to START condition time (bus free)

4.7

1.3

µs

Capacitive load for each bus line

400

STR750F Scheda tecnica(PDF) 61 Page - STMicroelectronics

STR750F Scheda tecnica(HTML) 61 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Scheda tecnica Scarica

Link URL