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STR750F Scheda tecnica(PDF) 43 Page - STMicroelectronics |
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STR750F Scheda tecnica(HTML) 43 Page - STMicroelectronics |
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43 / 73 page ![]() STR750F Electrical parameters 43/71 3.3.5 Clock and timing characteristics XT1 external Clock source Subject to general operating conditions for VDD_IO, and TA. Table 19. XT1 external Clock source Symbol Parameter Conditions(1) (2) 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. Min Typ Max Unit fXT1 External clock source frequency see Figure 20 460 MHz VXT1H XT1 input pin high level voltage 0.7xVDD_IO VDD_IO V VXT1L XT1 input pin low level voltage VSS 0.3xVDD_IO tw(XT1H) tw(XT1L) XT1 high or low time (3) 3. Data based on design simulation and/or technology characteristics, not tested in production. 6 ns tr(XT1) tf(XT1) XT1 rise or fall time (3) 5 IL XTx Input leakage current VSS ≤ VIN ≤ VDD_IO ±1 µA |
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