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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STR750F Scheda tecnica(PDF) 47 Page - STMicroelectronics |
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STR750F Scheda tecnica(HTML) 47 Page - STMicroelectronics |
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47 / 73 page  STR750F Electrical parameters 47/71 difference between N+1 consecutive clock rising edges and Tmin is the minimum time difference between N+1 consecutive clock rising edges. N should be kept sufficiently large to have a long term jitter (ex: thousands). For N=1, this becomes the single period jitter. See Figure 23 ● Cycle-to-cycle jitter (N period jitter) This corresponds to the time variation between adjacent cycles over a random sample of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1 to N. See Figure 24 Figure 23. Self-referred jitter (single and long term) Figure 24. Cycle-to-cycle jitter IDEAL CK_PLL trigger point ACTUAL CK_PLL nn+1 n+N --- long term jitter T single period jitter IDEAL CK_PLL ACTUAL CK_PLL nn+1 T Tcycle 1 Tcycle 2 n+2 --- Tcycle N-1 n+N |
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