STR750F datasheet(40/73 Pages) STMICROELECTRONICS

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Electrical parameters

STR750F

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Subject to general operating conditions for VDD_IO, and TA

Table 15.

Dual supply supply typical power consumption in Run, WFI, Slow and

Slow-WFI modes

To calculate the power consumption in Dual supply mode, refer to the values given in Table 14. and

consider that this consumption is split as follows:

IDD(single supply)~IDD(dual supply)= IDD_V18 + IDD(VDD_IO)

For 3.3V range: IDD(VDD_IO) ~ 1 to 2 mA

For 5V range: IDD(VDD_IO) ~ 2 to 3 mA

Therefore most of the consumption is sunk on the V18 power supply

This formula does not apply in STOP and STANDBY modes, refer to Table 16.

Table 16.

Typical power consumption in STOP and STANDBY modes

Symbol

Parameter

Conditions

3.3V

Typ(1)

Typ(2)

Unit

IDD

(3)

Supply current

in STOP

mode(4)

LP_PARAM bits: ALL OFF(5)

µA

LP_PARAM bits : MVREG ON, OSC4M OFF, FLASH

OFF(6)

130

135

LP_PARAM bits: MVREG ON, OSC4M ON , FLASH

OFF(6)

1950

1930

LP_PARAM bits: MVREG ON, OSC4M OFF, FLASH ON (6)

630

635

LP_PARAM bits: MVREG ON, OSC4M ON, FLASH ON (6)

2435

2425

Supply current

in STOP

mode(7)

LPPARAM bits: ALL OFF, with V18=1.8 V

IDD_V18

IDD_V33

µA

LP_PARAM bits: OSC4M ON, FLASH OFF

IDD_V18

IDD_V33

410

1475

410

1435

LP_PARAM bits: OSC4M OFF, FLASH ON

IDD_V18

IDD_V33

550

LP_PARAM bits: OSC4M ON, FLASH ON

IDD_V18

IDD_V33

910

1475

910

1445

Supply current

in STANDBY

mode(4)

RTC OFF

µA

RTC ON clocked by OSC32K

Typical data are based on TA=25°C, VDD_IO=3.3 V and V18=1.8 V unless otherwise indicated in the table.

Typical data are based on TA=25°C, VDD_IO=5.0 V and V18=1.8 V unless otherwise indicated in the table.

The conditions for these consumption measurements are described at the beginning of Section 3.3.4 on page 35.

Single supply scheme see Figure 12.

In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4 V, which significantly

reduces the leakage currents.

In this mode, the whole digital circuitry is powered internally by the MVREG at 1.8 V.

Dual supply scheme see Figure 13.

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