STR750F datasheet(5/73 Pages) STMICROELECTRONICS

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STR750F

Introduction

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1.1

Overview

The STR750 family includes devices in 2 package sizes: 64-pin and 100-pin. Both types

have the following common features:

ARM7TDMI-STM core with embedded Flash & RAM

STR750 family has an embedded ARM core and is therefore compatible with all ARM tools

and software. It combines the high performance ARM7TDMI-STM CPU with an extensive

range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-

speed single voltage FLASH memory and high-speed RAM.

Figure 1 shows the general block diagram of the device family.

Embedded Flash Memory

Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data.

An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to

be erased/programmed on-the-fly. This partitioning feature is ideal for storing application

parameters.

●

When configured in burst mode, access to Flash memory is performed at CPU clock

speed with 0 wait states for sequential accesses and 1 wait state for random access

(maximum 60 MHz).

●

When not configured in burst mode, access to Flash memory is performed at CPU

clock speed with 0 wait states (maximum 32 MHz)

Embedded SRAM

16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

Enhanced Interrupt Controller (EIC)

In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt

controller able to handle up to 32 vectors and 16 priority levels. This additional hardware

block provides flexible interrupt management features with minimal interrupt latency.

Serial Memory Interface (SMI)

The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It

communicates at a speed of up to 48 MHz. It can be used to access data, execute code

directly or boot the application from external memory. The memory is addressed as 4 banks

of up to 16 Mbytes each.

Clocks and start-up

After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an

internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application

code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its

stabilization time is monitored using a dedicated counter.

An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the

circuit automatically switches to the FREEOSC oscillator and an interrupt is generated.

In Run mode, the AHB and APB clock speeds can be set at a large number of different

frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32

MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM).

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