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Table 6-91. MMC0 Switching Characteristics – HS400 Mode

see Figure 6-76

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

200

MHz

HS4005

tc(clkH)

Cycle time, MMC0_CLK

HS4006

tw(clkH)

Pulse duration, MMC0_CLK high

2.24

HS4007

tw(clkL)

Pulse duration, MMC0_CLK low

2.24

HS4008

tosu(cmdV-clkH)

Output setup time, MMC0_CMD valid to MMC0_CLK rising edge(1)

2.58

HS4009

tosu(dV-clk)

Output setup time, MMC0_DAT[7:0] valid to MMC0_CLK rising or

falling edge(1)

0.60

HS40010

toh(clkH-cmdIV)

Output hold time, MMC0_CLK rising edge to MMC0_CMD invalid(2)

1.12

HS40011

toh(clk-dIV)

Output hold time, MMC0_CLK rising or falling edge to

MMC0_DAT[7:0] invalid(2)

0.85

(1)

This parameter defines the output setup time provided to the attached device. This time is relative to the next capture clock edge and

already includes the maximum propagation delay mismatch value defined in the MMC0 Timing Conditions table. The timing references

for this parameter are from mid-supply of the DAT or CMD signal transition to mid-supply of the CLK signal transition. The eMMC

standard defines the setup timing references from VIL or VIH of the DAT or CMD signal transition to mid-supply of the CLK signal

transition. Therefore, the system designer must consider the impact of the DAT signal slew rate when designing the PCB, and ensure

the time it takes for the DAT signal to slew from mid-supply to VIL or VIH does not erode the setup time margin.

(2)

This parameter defines the output hold time provided to the attached device. This time is relative to the previous launch clock edge and

already includes the maximum propagation delay mismatch value defined in the MMC0 Timing Conditions table. The timing references

for this parameter are from mid-supply of the CLK signal transition to mid-supply of the DAT or CMD signal transition. The eMMC

standard defines the hold timing references from mid-supply of the CLK signal transition to VIL or VIH of the DAT or CMD signal

transition. Therefore, the system designer must consider the impact of the DAT signal slew rate when designing the PCB, and ensure

the time it takes for the DAT signal to slew from VIL or VIH to mid-supply does not erode the hold time margin.

MMC0 CLK

MMC0 CMD

MMC0 DAT7

[ :0]

H 40010

H 4009

H 4005

H 4006

H 4007

H 40011

H 4009

H 40011

H 4008

Figure 6-76. eMMC in – HS400 Mode – Transmitter Mode

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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