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Table 6-115. OSPI Switching Characteristics – PHY Data Training

See Figure 6-97 and Figure 6-98

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

1.8V, DDR

6.0

3.3V, DDR

7.5

1.8V, SDR

6.0

3.3V, SDR

7.5

tw(CLKL)

Pulse duration, OSPI0_CLK low

DDR

((0.475P(1)) - 0.3)

SDR

tw(CLKH)

Pulse duration, OSPI0_CLK high

DDR

((0.475P(1)) - 0.3)

SDR

td(CSn-CLK)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

DDR

((0.475P(1)) +

(0.975M(2)R(4)) +

(0.04TD(5)) - 1)

((0.525P(1)) +

(1.025M(2)R(4)) +

(0.11TD(5)) + 1)

O10

SDR

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

DDR

((0.475P(1)) +

(0.975N(3)R(4)) -

(0.04TD(5)) - 1)

((0.525P(1)) +

(1.025N(3)R(4)) -

(0.11TD(5)) + 1)

O11

SDR

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

DDR

(6)

O12

SDR

tDIVW

Data invalid window (O6 Max - Min)

DDR

1.6

Data invalid window (O12 Max - Min)

SDR

(1)

P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = reference clock cycle time in ns

(5)

TD = PHY_CONFIG_TX_DLL_DELAY_FLD

(6)

Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data

valid window. The tDIVW parameter defines the maximum data invalid window. This parameter is provided in lieu of minimum and

maximum delay times, where it must be used to check compatibility with the data valid window requirements of an attached device.

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 6-97. OSPI0 Switching Characteristics – PHY DDR Data Training

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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