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6.9.5.19.1.2 OSPI0 Without Data Training

Note

Timing parameters defined in this section are only applicable when data training is not implemented

and DLL delays are configured as described in Section 6.9.5.19.1.2.1 and Section 6.9.5.19.1.2.2.

6.9.5.19.1.2.1 OSPI0 PHY SDR Timing

Table 6-116 defines DLL delays required for OSPI0 PHY SDR Mode. Table 6-117, Figure 6-99, Figure 6-100,

Table 6-118, and Figure 6-101 present timing requirements and switching characteristics for OSPI0 PHY SDR

Mode.

Table 6-116. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD,

0x0

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

Table 6-117. OSPI0 Timing Requirements – PHY SDR Mode

see Figure 6-99 and Figure 6-100

NO.

MODE

MIN

MAX

UNIT

O19

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

1.8V, SDR with Internal PHY Loopback

4.8

3.3V, SDR with Internal PHY Loopback

5.19

O20

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

1.8V, SDR with Internal PHY Loopback

-0.5

3.3V, SDR with Internal PHY Loopback

-0.5

O21

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

1.8V, SDR with External Board Loopback

0.6

3.3V, SDR with External Board Loopback

0.9

O22

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

1.8V, SDR with External Board Loopback

1.7

3.3V, SDR with External Board Loopback

2.0

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_05

O 9

O20

Figure 6-99. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback

OSPI_DQS

OSPI_TIMING_06

O21

O 2

OSPI_D[i:0]

Figure 6-100. OSPI0 Timing Requirements – PHY SDR with External Board Loopback

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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