MK50H28DIP datasheet(20/64 Pages) STMICROELECTRONICS

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UPRIM

< 3:0 >

PPRIM

< 3:0 >

4.1.2.2 Control and Status Register 1 (CSR1)

RAP <3:1> = 133/

BIT

NAME

DESCRIPTION

UERR

USER PRIMITIVE ERROR is set by the MK50H28 when a primitive is issued by the

user which is in conflict with the current status of the chip. UERR is READ/CLEAR

ONLY and is set by MK50H28 and cleared by writing a ”1” into the bit. Writing a ”0” in

this bit has no effect. It is also cleared by Bus RESET.

UAV

USER PRIMITIVE AVAILABLE is set by the user when a primitive is written into UPRIM.

It is cleared by the MK50H28 after the primitive has been processed. This bit is also

cleared by a Bus RESET.

13:12

UPARM

USER PARAMETER is written by the host in conjunction with the user primitives in

UPRIM. This User Parameter field provides information to the MK50H28 concerning the

corresponding user primitive. NOTE: For all primitives UPARM = 0 unless otherwise

indicated.

11:08

UPRIM

USER PRIMITIVE is written by the user, in conjunction with setting UAV, to control the

MK50H28 link procedures. The following primitives are available:

Stop: Causes MK50H28 to enter the STOPPED Phase. All link activity is terminated

and the STOP bit is set. All DMA activity ceases. The transmitter outputs all ones, and all

received data is ignored.

Start: Instructs the MK50H28 to exit the STOPPED Phase and enter the INFORMATION

TRANSFER Phase. The Context Table and the Descriptor Rings are Reset. The

transmitter begins to output flags. The Start primitive is valid only after the device is

initialized (Init Request performed.) If the Auto LMI primitive is not issued after a Start

primitive, then the only way to transmit LMI frames is through the use of LMI

primitives (10, 11, 12, & 14), and processing is performed on received LMI frames,

but no automatic response or action is taken. Valid only in STOPPED phase.

Init Request: Instructs the MK50H28 to read the Initialization Block from memory. This

should be performed prior to the Start primitive or Transparent primitive after a bus reset

or power-up. Valid only in STOPPED phase.

Transparent Mode: Instructs the device to exit the STOPPED Phase, enter the

TRANSPARENT Phase, and reset the Context Table and Descriptor Rings. No header

stripping or pre-pending is done for any DLCI channel, and no automatic LMI processing

is possible in this mode. All frames are received to Context Table entry 0 associated

descriptor ring and buffers, and the RTAN bit in CT0 should be set so that the entire

received frame will be written to the buffer. Transmission of frames can occur from

any Context Table entry, including CT0, and the XTRAN bit should be set so that

only the data in the buffer will be transmitted for the entire frame. This primitive is only

valid after device Initialization (Init Request performed). Valid only in STOPPED phase.

Status Request: Instructs the MK50H28 to write the current chip status into the

STATUS BUFFER. Valid in all states, but only after the Init primitive has been previously

issued.

Self-Test Request: Instructs the MK50H28 to perform the built in internal self test. Valid

only in the STOPPED Phase. See section 4.4.10 for the self test procedure.

MK50H28

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