MK50H28DIP datasheet(47/64 Pages) STMICROELECTRONICS

47 / 64 page

4.4.2.3 Bi-directional Procedures (Auto LMI Mode) - Continued

3. After every nN1/N391 transmissions of STATUS ENQUIRY with Report Type of ”LIV Only”, the

MK50H28 transmits a STATUS ENQUIRY with Report Type of ”Full Status”.

4. A received Full STATUS frame will be stored into the LMI channel buffer, the sequence number

checking will be performed, and its reception will be indicated to the host via Provider Primitive

13. A received Asynchronous STATUS frame will be stored into the LMI channel buffer and its

reception will be indicated to the host via Provider Primitive 14.

5. The MK50H28 also automatically responds to a STATUS ENQUIRY (”LIV Only”) frame received

by transmitting a STATUS (”LIV Only”) frame along with restarting the nT2 timer. When a ”Full

Status” STATUS ENQUIRY is received, the device issues the LMI Received primitive 13 (with

PPARM=1) and expects the host to respond with LMI Status Request Primitive 11 with

UPARM=0 (when ready to transmit the Full STATUS frame).

6. Asynchronous STATUS frames may be transmitted by placing the data to be transmitted into the

appropriate buffer and issueing Primtive 11 with UPARM=2.

4.4.3 Sending Data On A Link

Use the following procedure to send a frame:

1. Make sure that ACTIVE bit in the ALT and TXRDY bit in the CT are set for that channel.

2. Make sure that the Transmit Ring Pointer, Current Transmit Descriptor and address field infor-

mation in the CT is valid.

3. Wait for the OWNA bit of the current transmit descriptor to be cleared, if it is not already.

4. Fill the buffer associated with the current transmit descriptor with the data to be sent, or set the

descriptor buffer address to any already filled buffer.

5. Repeat steps 3 & 4 for next buffer if chaining is necessary, setting ELF & MCNT appropriately.

6. Set the OWNA bit for each descriptor to be used in sending the frame.

7. Go on to next descriptor. The MK50H28 will clear OWNA bits when the frame has been transmitted.

4.4.4 Receiving Data On A Link

The following procedure should be followed when receiving a frame:

1. Make sure that ACTIVE bit in the ALT and RXRDY bit in the CT are set for that channel.

2. Make sure that the Index to CT in the ALT points to appropriate CT entry for that channel.

3. Also make sure that the Receive Ring Pointer, Current Receive Descriptor information in the CT

is valid.

4. Make sure the OWNA bit of the current receive descriptor is clear.

5. A Receive Interrupt (RINT) will indicate reception of a frame.

6. Read the entry or entries in the Receive Interrupt Descriptor Ring that have the SRVC bit set.

The Receive Context Table Address and Current Receive Descriptor index available here indi-

cate the CT entry and the descriptor within the Rx Ring associated with the received frame.

6. Read data out of the buffer associated with the current receive descriptor.

8. Set the OWNA bit of the current receive descriptor to return ownership to the MK50H28.

9. If the ELF bit of the current receive descriptor is clear, then go on to the next descriptor and re-

peat from step 4 appending data from each buffer until a descriptor with ELF=1 is reached.

10. LMI frames received in any mode will not cause Receive Interrupts (RINT) to be generated, nor

will the Receive Interrupt Ring be updated. Instead, the MK50H28 will issue primitives corre-

sponding to the received LMI Frames which are not automatically processed by the MK50H28

(i.e. non ”LIV only” frames). See the description of primitives in section 4.1.2.2.

11. For frames received on the LMI Channel (typically DLCI 0), bits 09-11 of the Receive Message

Descriptor 0 (RMD0) for the LMI channel will indicate the type of frame received. A setting of

000 indicates a received SVC frame or Transparent Mode frame. See section 4.3.1.2 for details.

MK50H28

47/64

MK50H28DIP Scheda tecnica(PDF) 47 Page - STMicroelectronics

MK50H28DIP Scheda tecnica(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Scheda tecnica Scarica

Link URL