MK50H28DIP datasheet(38/64 Pages) STMICROELECTRONICS

38 / 64 page

4.2.9 Priority DLCI Block

The Priority DLCI Block (PDB) is a mechanism through which the host can demand the MK50H28 to im-

mediately service certain desired DLCIs. The host should first set up entries in the PDB before setting

the PTDMD bit in CSR2. In response to that, the MK50H28, after completing transmission service of its

current DLCI, will jump to the PDB rather than advancing to the next entry in the Context Table. After

servicing all active entries in the PDB, the MK50H28 will return to the Context Table and resume the

transmission service that was in progress before it was interrupted. (NOTE: A maximum of 256 entries

are allowed in the PDB.) The following is the format of the Priority DLCI Block.

Index to Context Table

MSB

LSB

Index to Context Table

IADR + 96

IADR + 98

IADR + XX

(0)

(1)

4.3 Receive and Transmit Descriptor Rings

Each active channel has an associated transmit and receive ring (Figure 3). Each ring can have a maxi-

mum of 128 descriptors, and each descriptor in the ring is a 4 word entry. Each ring is terminated by set-

ting the EOR bit in the last descriptor. Except for the first word (see below for RMD0 or TMD0), all the

descriptors are identical for both LMI and non-LMI channels. NOTE: The Buffer Byte Count (BMCT) for

LMI channels should be greater than 14 bytes. The following is the format of the receive and transmit de-

scriptors.

BIT

NAME

DESCRIPTION

Index to CT

13-bit index into Context Table

Reserved. Must be written as zeros.

EOPCH

End of PDB. Setting this bit to 1 indicates that this is the last entry in the PDB

ACTIVE

This bit is set by the host if the corresponding index into the Context Table is active. The

MK50H28 ignores the entry if this bit is not set.

MK50H28

38/64

MK50H28DIP Scheda tecnica(PDF) 38 Page - STMicroelectronics