MK50H28DIP datasheet(23/64 Pages) STMICROELECTRONICS

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BIT

NAME

DESCRIPTION

CYCLE

Setting this bit selects a shorter DMA Cycle (5 vs 6 SYSCLK)

EIBEN

Extended Initialization Block Enable. Setting this bit causes the MK50H28

to use an

extended Initialization Block which uses all of IADR+08 as a 16-bit scaler and moves nN1

to the upper byte of IADR+40.

DLCI1K

Setting this bit causes the chip to recognize the 8192 possible DLCIs.If this bit is cleared,

the chip will ignore all received frames with DLCI greater than 1023.

LMICH

CHLMI Channel Select: Setting this bit to 0 causes frames received on DLCI 0 to be

treated as LMI frames.. Setting it to 1 causes frames received on DLCI 1023 to be treated

as LMI frames. NOTE: Regardless of the setting of this bit, only the first entry in the

Context Table table (CT0) will be used for transmission and reception of LMI

frames.

TRAN

Should be set only if frames need to be transmitted without protocol processing from the

transmit buffers. With this bit set, the chip will not prepend an address field when

transmitting data from the buffers, but rather, the buffers should have both address and

data information for proper Frame Relay protocol.

Reserved. Must be written as zeroes.

ANXD

Setting this bit enables operation in conformance with T1.617 Annex D specifications.

With ANXD=0, the MK50H28 operates in conformance with CCITTQ.933 Annex A.

TDMD

Transmit Demand. Setting this bit causes the MK50H28 to ignore the TP (Transmit Poll

timer) and continuously poll all Context Table entries until TDMD is cleared by the host.

07:00

IADR

The high order 8 bits of the address of the first word in the Initialization Block. IADR must

be written by the Host prior to issuing an Init Request primitive.

4.1.2.3 Control and Status Register 2 (CSR2)

RAP<3:1> = 2

IADR<23:16>

4.1.2.4 Control and Status Register 3 (CSR3)

RAP<3:1>

IADR <15:00>

BIT

NAME

DESCRIPTION

15:00

IADR

The low order 16 bits of the address of the first word in the Initialization Block. Must be

written by the Host prior to issuing an Init Request primitive. The Initialization block must

begin on a word boundary.

MK50H28

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