MK50H28DIP datasheet(34/64 Pages) STMICROELECTRONICS

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WORD

NAME

DESCRIPTION

CT+14

SRIP

Shared Receive Descriptro Ring Index Pointer. This field contains the Index Pointer to the

CT entry with the CURRD and RDRA (CTADR+14, +16) to be used for received frames

rather than the CURRD & RDRA specified in the current CT entry, if SRIPE = 1. All 13

bits of this field will be used to index into the CT, regardless of DLCI1K setting in CSR2.

SRIPE(00)

SRIP Enable. When set, this bit enables the sharing of one Receive Descriptor Ring

by many DLCIs or CT entries. When SRIPE=1, the Receive Descriptor Ring and buffer

associated with the CURRD and RDRA values in the CT entry pointed to by the SRIP

Index Pointer will be used for the received frame rather than the CURRD and RDRA

values in the current CT entry associated with the DLCI of the received frame. The

RCCNT & XCCNT used will also be those in the CT entry pointed to by the SRIP.

CT+16

CURRD

(15:8)

Specifies the current receive descriptor in the ring (0 - 127 in the upper 7 bits). This field

should initially be written with zeroes.

CT+16,+18

RDRA

Starting address of the Receive Descriptor Ring for a channel. It must be word aligned.

CT+20

Rcv FECNs

Counter for keeping track of the FECNs received when a channel is ready.

Rcv BECNs

Counter for keeping track of the BECNs received when a channel is ready.

CT+22

Rcv DEs

Counter for keeping track of the DEs received when a channel is ready.

Discard

Frames

Counter for keeping track of received frames with DE = 1 that are discarded due to

congestion on a channel. Incremented for LMI frames is received on CT0 inconsistent

with the operating mode. (Stop or Re-Initialization will not reset this nor any CT Counter.)

CT+24

RCCNT

RX Congestion Counter. This counter is incremented each time a received frame is

placed into the RX descriptor Ring for that channel. The MK50H28 does this just prior to

clearing the OWNA bit(s) for the descriptor(s) corresponding to each received frame.

NOTE: This counter should be programmed with an initial value of 00. It is the

responsibility of the host processor to decrement and/or reset this counter as needed to

do Receive Descriptor Ring congestion monitoring

XCCNT

TX Congestion Counter. This counter is incremented each time a frame is transmitted

from the TX descriptor Ring for that channel. The MK50H28 does this just prior to clearing

the OWNA bit(s) for the descriptor(s) corresponding to each tranmitted frame.

NOTE: It is the responsibility of the host processor to program this counter with the 2’s

complement value of the number of descriptors that it filled with frame data to be

transmitted, if Transmit Descriptor Ring congestion monitoring is needed.

CT+26

RGF Cnt

Received Good Frames Counter. (Stop or Re-Init will not reset this nor any CT Counter.)

CT+28 - 31

Reserved. Must be written as zeros.

4.2.5 Interrupt Descriptor Ring Addresses

IADR + 24

IADR + 26

TINTADR <15:00>

TINTADR <23:16>

RESERVED

IADR + 28

IADR + 30

RINTADR <15:0 0>

RINTADR <23:16>

RESERVED

BIT

NAME

DESCRIPTION

15:08

Reserved, must be written as a zero.

07:00/15:00

TINTADR

Transmit Interrupt Descriptor Ring Address. (Must begin on a word boundary).

07:00/15:00

RINTADR

Receive Interrupt Descriptor Ring Address. (Must begin on a word boundary).

MK50H28

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