H8SSLASH2218 datasheet(328/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 280 of 698

REJ09B0074-0600

Table 9.3

CCLR2 to CCLR0 (channel 0)

Bit 7

Bit 6

Bit 5

Channel

CCLR2

CCLR1

CCLR0

Description

TCNT clearing disabled

TCNT cleared by TGRA compare

match/input capture

TCNT cleared by TGRB compare

match/input capture

TCNT cleared by counter clearing for

another channel performing synchronous

clearing/synchronous operation*

TCNT clearing disabled

TCNT cleared by TGRC compare

match/input capture*

TCNT cleared by TGRD compare

match/input capture*

TCNT cleared by counter clearing for

another channel performing synchronous

clearing/synchronous operation*

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register. TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture dose not occur.

Table 9.4

CCLR2 to CCLR0 (channels 1 and 2)

Bit 7

Bit 6

Bit 5

Channel

Reserved*

CCLR1

CCLR0

Description

1, 2

TCNT clearing disabled

TCNT cleared by TGRA compare

match/input capture

TCNT cleared by TGRB compare

match/input capture

TCNT cleared by counter clearing for

another channel performing synchronous

clearing/synchronous operation*

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.

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