H8SSLASH2218 datasheet(331/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 283 of 698

REJ09B0074-0600

Bit

Bit Name Initial value

R/W

Description

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal way,

or TGRA and TGRC are to be used together for buffer

operation. When TGRC is used as a buffer register,

TGRC input capture/output compare is not generated. In

channels 1 and 2, which have no TGRC, bit 4 is reserved.

It is always read as 0 and cannot be modified.

0: TGRA operates normally

1: TGRA and TGRC used together for buffer operation

MD3

MD2

MD1

MD0

R/W

Modes 3 to 0

These bits are used to set the timer operating mode.

MD3 is a reserved bit. In a write, the write value should

always be 0. See table 9.8, for details.

Table 9.8

MD3 to MD0

Bit 3

Bit2

Bit 1

Bit 0

MD3*

MD2*

MD1

MD0

Description

Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

Legend:

×: Don’t care

Notes: 1. MD3 is reserved bit. In a write, it should be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always

be written to MD2.

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