H8SSLASH2218 datasheet(341/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 293 of 698

REJ09B0074-0600

9.3.4

Timer Interrupt Enable Register (TIER)

The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU

has three TIER registers, one for each channel.

Bit

Bit Name Initial value

R/W

Description

TTGE

R/W

A/D Conversion Start Request Enable

Enables or disables generation of A/D conversion start

requests by TGRA input capture/compare match.

0: A/D conversion start request generation disabled

1: A/D conversion start request generation enabled

–

Reserved

This bit is always read as 1 and cannot be modified.

TCIEU

R/W

Underflow Interrupt Enable

Enables or disables interrupt requests (TCU) by the TCFU

flag when the TCFU flag in TSR is set to 1 in channels 1

and 2. In channel 0, bit 5 is reserved.

0: Interrupt requests (TCIU) by TCFU disabled

1: Interrupt requests (TCIU) by TCFU enabled

TCIEV

R/W

Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the

TCFV flag when the TCFV flag in TSR is set to 1.

0: Interrupt requests (TCIV) by TCFV disabled

1: Interrupt requests (TCIV) by TCFV enabled

TGIED

R/W

TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in channel

0. In channels 1 and 2, bit 3 is reserved. It is always read

as 0 and cannot be modified.

0: Interrupt requests (TGID) by TGFD disabled

1: Interrupt requests (TGID) by TGFD enabled.

TGIEC

R/W

TGR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by the

TGFC bit when the TGFC bit in TSR is set to 1 in channel

0. In channels 1 and 2, bit 2 is reserved. It is always read

as 0 and cannot be modified.

0: Interrupt requests (TGIC) by TGFC disabled

1: Interrupt requests (TGIC) by TGFC enabled

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