H8SSLASH2218 datasheet(345/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 297 of 698

REJ09B0074-0600

9.3.6

Timer Counter (TCNT)

The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel.

The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The

TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

9.3.7

Timer General Register (TGR)

The TGR registers are 16-bit registers with a dual function as output compare and input capture

registers. The TPU has 16 TGR registers, four each for channel 0 and two each for channels 1 and

2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers. The

TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.

9.3.8

Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2.

When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT

counter.

Bit

Bit Name Initial Value

R/W

Description

7 to

–

All 0

–

Reserved

The write value should always be 0.

CST2

CST1

CST0

R/W

Counter Start 2 to 0 (CST2 to CST0)

These bits select operation or stoppage for TCNT.

If 0 is written to the CST bit during operation with the

TIOC pin designated for output, the counter stops but the

TIOC pin output compare output level is retained.

If TIOR is written to when the CST bit is cleared to 0, the

pin output level will be changed to the set initial output

value.

0: TCNT_2 to TCNT_0 count operation is stopped

1: TCNT_2 to TCNT_0 performs count operation

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