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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2218 Scheda tecnica(PDF) 357 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 357 Page - Renesas Technology Corp |
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357 / 750 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Jun. 03, 2008 Page 309 of 698 REJ09B0074-0600 9.5.3 Buffer Operation Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 9.17 shows the register combinations used in buffer operation. Table 9.17 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.16. Buffer register Timer general register TCNT Comparator Compare match signal Figure 9.16 Compare Match Buffer Operation • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9.17. Buffer register Timer general register TCNT Input capture signal Figure 9.17 Input Capture Buffer Operation |
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