H8SSLASH2218 datasheet(361/750 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 313 of 698

REJ09B0074-0600

9.5.4

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be

selected as the output level in response to compare match of each TGR. Settings of TGR registers

can output a PWM waveform in the range of 0

% to 100 % duty. Designating TGR compare match

as the counter clearing source enables the period to be set in that register. All channels can be

designated for PWM mode independently. Synchronous operation is also possible. There are two

PWM modes, as described below.

• PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is

output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified

by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The

initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are

identical, the output value does not change when a compare match occurs. In PWM mode 1, a

maximum 4-phase PWM output is possible.

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty registers.

The output specified in TIOR is performed by means of compare matches. Upon counter

clearing by a synchronization register compare match, the output value of each pin is the initial

value set in TIOR. If the set values of the cycle and duty registers are identical, the output

value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase

PWM output is possible by combined use with synchronous operation. The correspondence

between PWM output pins and registers is shown in table 9.18.

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