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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2218 Scheda tecnica(PDF) 380 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 380 Page - Renesas Technology Corp |
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380 / 750 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Jun. 03, 2008 Page 332 of 698 REJ09B0074-0600 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.45 shows the timing in this case. Counter clear signal Write signal Address φ TCNT address TCNT TCNT write cycle T 1 T 2 N H'0000 Figure 9.45 Contention between TCNT Write and Clear Operations Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.46 shows the timing in this case. TCNT input clock Write signal Address φ TCNT address TCNT TCNT write cycle T 1 T 2 N M TCNT write data Figure 9.46 Contention between TCNT Write and Increment Operations |
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