H8SSLASH2218 datasheet(384/750 Pages) RENESAS

Il numero della parte	H8S/2218

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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384 / 750 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 336 of 698

REJ09B0074-0600

Contention between Buffer Register Write and Input Capture: If the input capture signal is

generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and

the write to the buffer register is not performed. Figure 9.51 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

Buffer register write cycle

TGR

Buffer

Buffer register

address

Figure 9.51 Contention between Buffer Register Write and Input Capture

Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and

counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing

takes precedence. Figure 9.52 shows the operation timing when a TGR compare match is specified

as the clearing source, and H'FFFF is set in TGR.

Counter

clearing signal

TCNT input

clock

TCNT

TGF flag

Prohibited

TCFV flag

H'FFFF

H'0000

Figure 9.52 Contention between Overflow and Counter Clearing

H8S/2218 Scheda tecnica(PDF) 384 Page - Renesas Technology Corp