H8SSLASH2218 datasheet(394/750 Pages) RENESAS

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Section 10 Watchdog Timer (WDT)

Rev.6.00 Jun. 03, 2008 Page 346 of 698

REJ09B0074-0600

10.5

Usage Notes

10.5.1

Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write to. The procedures for writing to and reading these registers are given

below.

Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.

They cannot be written to with byte transfer instructions. Figure 10.6 shows the format of data

written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to

TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the

write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the

lower byte must contain the write data. This transfers the write data from the lower byte to TCNT

or TCSR.

TCNT write

TCSR write

Address: H'FF74

H'5A

Write data

8 7

H'A5

Write data

8 7

Figure 10.6 Format of Data Written to TCNT and TCSR

Writing to RSTCSR: RSTCSR must be written to by a word transfer to address H'FF76. It cannot

be written to with byte instructions. Figure 10.7 shows the format of data written to RSTCSR. The

method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits.

To write 0 to the WOVF bit, the upper byte of the written word must contain H'A5 and the lower

byte must contain H'00. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS

bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte

must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE

and RSTS bits, but has no effect on the WOVF bit.

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