H8SSLASH2218 datasheet(392/750 Pages) RENESAS

Il numero della parte	H8S/2218

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 10 Watchdog Timer (WDT)

Rev.6.00 Jun. 03, 2008 Page 344 of 698

REJ09B0074-0600

10.3.2

Timing of Setting of Watchdog Timer Overflow Flag (WOVF)

With WDT, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If

TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated

for the entire chip. This timing is illustrated in figure 10.3.

TCNT

H'FF

H'00

Overflow signal

(internal signal)

Internal reset

signal

WOVF

518 states (WDT0)

Figure 10.3 Timing of WOVF Setting

10.3.3

Interval Timer Mode

To use the WDT as an interval timer, clear bit WT/

IT in TCSR to 0 and set bit TME to 1. When

the interval timer is operating, an interval timer interrupt (WOVI) is generated each time the

TCNT overflows. Therefore, an interrupt can be generated at intervals.

TCNT count

H'00

Time

H'FF

WT/

IT = 0

TME = 1

WOVI

Overflow

WOVI: Interval interrupt request generation

Legend:

WOVI

Figure 10.4 Operation in Interval Timer Mode

H8S/2218 Scheda tecnica(PDF) 392 Page - Renesas Technology Corp