H8SSLASH2218 datasheet(472/750 Pages) RENESAS

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Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 424 of 698

REJ09B0074-0600

12.6.4

Serial Data Reception (Clocked Synchronous Mode)

Figure 12.21 shows an example of SCI operation for reception in clocked synchronous mode. In

serial reception, the SCI operates as described below.

1. The SCI performs internal initialization synchronous with a synchronous clock input or output,

starts receiving data, and stores the received data in RSR.

2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag

in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this

time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the

RDRF flag remains to be set to 1.

3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is

generated. Continuous reception is possible because the RXI interrupt routine reads the receive

data transferred to RDR before reception of the next receive data has finished.

Bit 7

Serial data

Synchronization

clock

1 frame

RDRF

ORER

ERI interrupt request

generated by overrun

error

RXI interrupt request

generated

RDR data read and

RDRF flag cleared to 0

in RXI interrupt service

routine

RXI interrupt

request

generated

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

Figure 12.21 Example of SCI Operation in Reception

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,

FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.22 shows a sample flow chart

for serial data reception.

When the internal clock is selected during reception, the synchronization clock will be output until

an overrun error occurs or the RE bit is cleared. To receive data in frame units, a dummy data of

one frame must be transmitted simultaneously.

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