H8SSLASH2218 datasheet(586/750 Pages) RENESAS

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Section 15 A/D Converter

Rev.6.00 Jun. 03, 2008 Page 538 of 698

REJ09B0074-0600

15.3.1

A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of

A/D conversion. The ADDR registers, which store a conversion result for each channel, are

shown in table 15.2.

The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.

The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. The

temporary register contents are transferred from the ADDR when the upper byte data is read.

When reading the ADDR, read the upper byte before the lower byte, or read in word unit. The

initial value of the ADDR is H'0000.

Table 15.2

Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

A/D Data Register to Be Stored the Results of A/D Conversion

AN0

ADDRA

AN1

ADDRB

AN2, AN14

ADDRC

AN3, AN15

ADDRD

15.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.

Bit

Bit Name Initial Value

R/W

Description

ADF

R/(W)* A/D End Flag

A status flag that indicates the end of A/D conversion.

[Setting conditions]

•

When A/D conversion ends in single mode

•

When A/D conversion ends on all channels

specified in scan mode

[Clearing conditions]

• When 0 is written after reading ADF = 1

• When DMAC is activated by an ADI interrupt and

ADDR is read

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