H8SSLASH2218 datasheet(592/750 Pages) RENESAS

Il numero della parte	H8S/2218

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 15 A/D Converter

Rev.6.00 Jun. 03, 2008 Page 544 of 698

REJ09B0074-0600

15.5.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then

starts conversion. Figure 15.5 shows the A/D conversion timing. Tables 15.3 and 15.4 show the

A/D conversion time.

As indicated in figure 15.5, the A/D conversion time (tCONV) includes tD and the input sampling

time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The

total conversion time therefore varies within the ranges indicated in table 15.4.

In scan mode, the values given in table 15.4 apply to the first conversion time. The values given in

table 15.3 apply to the second and subsequent conversions.

(1)

(2)

SPL

CONV

Address

Write signal

Input sampling

timing

ADF

Legend:

(1):

ADCSR write cycle

(2):

ADCSR address

A/D conversion start delay

SPL:

Input sampling time

CONV:

A/D conversion time

Figure 15.5 A/D Conversion Timing

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