H8SSLASH2218 datasheet(105/750 Pages) RENESAS

105 / 750 page

Section 2 CPU

Rev.6.00 Jun. 03, 2008 Page 57 of 698

REJ09B0074-0600

2.6.2

Basic Instruction Formats

The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op), a register field (r), an effective address extension (EA), and a condition field

(cc).

Figure 2.11 shows examples of instruction formats.

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.

Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or

4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branching condition of Bcc instructions.

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

EA(disp)

BRA d:16, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

(4) Operation field, effective address extension, and condition field

Figure 2.11 Instruction Formats (Examples)

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