H8SSLASH2218 datasheet(106/750 Pages) RENESAS

106 / 750 page

Section 2 CPU

Rev.6.00 Jun. 03, 2008 Page 58 of 698

REJ09B0074-0600

2.7

Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR,

BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in

the operand.

Table 2.11

Addressing Modes

No. Addressing Mode

Symbol

@ERn

@(d:16,ERn)/@(d:32,ERn)

@ERn+

@–ERn

Absolute address

@aa:8/@aa:16/@aa:24/@aa:32

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect

@@aa:8

2.7.1

The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the

operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7

can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2

The register field of the instruction code specifies an address register (ERn) which contains the

address of the operand on memory. If the address is a program instruction address, the lower 24

bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

H8S/2218 Scheda tecnica(PDF) 106 Page - Renesas Technology Corp