H8SSLASH2218 datasheet(204/750 Pages) RENESAS

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Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 156 of 698

REJ09B0074-0600

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the operations.

• If the CPU is in sleep mode, it transfers the bus immediately.

DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is

generated.

In the case of a USB request in short address mode or normal mode, and in cycle steal mode, the

DMAC releases the bus after a single transfer.

In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after

completion of the transfer.

6.10.3

External Bus Release Usage Note

External bus release can be performed on completion of an external bus cycle in the H8S/2218

Group. The

CS signal remains low until the end of the external bus cycle. Therefore, when

external bus release is performed, the

CS signal may change from the low level to the high-

impedance state.

6.11

Resets and the Bus Controller

In a power-on reset, this LSI, including the bus controller, enters the reset state at that point, and an

executing bus cycle is discontinued.

In a manual reset*, the bus controller's registers and internal state are maintained, and an executing

external bus cycle is completed. In this case,

WAIT input is ignored and write data is not

guaranteed.

Note: * Supported only by the H8S/2218 Group.

H8S/2218 Scheda tecnica(PDF) 204 Page - Renesas Technology Corp