H8SSLASH2218 datasheet(245/750 Pages) RENESAS

Il numero della parte	H8S/2218

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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245 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 197 of 698

REJ09B0074-0600

7.4.9

DMAC Bus Cycles (Dual Address Mode)

Short Address Mode: Figure 7.15 shows a transfer example in which

TEND* output is enabled

and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external

8-bit, 2-state access space to internal I/O space.

DMA read

HWR

TEND*

LWR

DMA write

DMA read DMA write

DMA read

DMA write

DMA

dead

Address bus

Note: * This LSI does not support

TEND output.

Bus release

Last transfer cycle

Figure 7.15 Example of Short Address Mode Transfer

A one-byte or one-word transfer is performed for one transfer request, and after the transfer the

bus is released. While the bus is released one or more bus cycles are inserted by the CPU.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

In repeat mode, when

TEND* output is enabled, TEND* output goes low in the transfer cycle in

which the transfer counter reaches 0.

Note: * This LSI does not support

TEND output.

H8S/2218 Scheda tecnica(PDF) 245 Page - Renesas Technology Corp