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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2218 Scheda tecnica(PDF) 250 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 250 Page - Renesas Technology Corp |
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250 / 750 page  Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 202 of 698 REJ09B0074-0600 7.4.10 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.9 summarizes the priority order for DMAC channels. Table 7.9 DMAC Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B Low If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest- priority channel from among those issuing a request according to the priority order shown in table 7.9. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.20 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA read DMA write DMA read DMA write DMA read DMA write DMA read φ Address bus RD HWR LWR DMA control Channel 0A Channel 0B Channel 1 Idle Write Idle Read Write Idle Read Write Read Request clear Request hold Request hold Request clear Request clear Bus release Channel 0A transfer Bus release Channel 0B transfer Channel 1 transfer Bus release Request hold Read Selection Non- selection Selection Figure 7.20 Example of Multi-Channel Transfer |
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