H8SSLASH2218 datasheet(251/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 203 of 698

REJ09B0074-0600

7.4.11

Relation between the DMAC and External Bus Requests

There can be no break between a DMA cycle read and a DMA cycle write. This means that an

external bus release cycle is not generated between the external read and external write in a DMA

cycle.

In the case of successive read and write cycles, such as in burst transfer or block transfer, an

external bus released state may be inserted after a write cycle.

When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these

DMA cycles can be executed at the same time as refresh cycles or external bus release. However,

simultaneous operation may not be possible when a write buffer is used.

7.4.12

NMI Interrupts and DMAC

When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An

NMI interrupt does not affect the operation of the DMAC in other modes.

In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit

are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.

If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on

completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the

CPU.

The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.

Figure 7.21 shows the procedure for continuing transfer when it has been interrupted by an NMI

interrupt on a channel designated for burst mode transfer.

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