H8SSLASH2218 datasheet(256/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 208 of 698

REJ09B0074-0600

If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC

[1]

[2]

Note:

The lower word of MAR is the updated value after the operation in [1].

CPU longword read

DMA transfer cycle

MAR upper

word read

MAR lower

word read

DMA read

DMA write

DMA internal

address

DMA control

DMA register

operation

Idle

Read

Write

Idle

Transfer

source

Transfer

destination

Figure 7.26 Contention between DMAC Register Update and CPU Read

7.6.2

Module Stop

When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state

is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is

enabled. This setting should therefore be made when DMAC operation is stopped.

When the DMAC clock stops, DMAC register accesses can no longer be made. Since the

following DMAC register settings are valid even in the module stop state, they should be

invalidated, if necessary, before a module stop.

• Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)

For details, refer to section 20, Power-Down Modes.

7.6.3

Medium-Speed Mode

When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-

detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip

peripheral modules operate on a high-speed clock.

Consequently, if the period in which the relevant interrupt source is cleared by the CPU or another

DMAC channel, and the next interrupt is generated, is less than one state with respect to the

DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be

ignored.

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