7733 datasheet(558/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21-10

Appendix 3. Control registers

The control registers allocated in the SFR area are shown on the following pages.

Below is the structure diagram for all registers.

XXX register (address XX16)

... select bit

0 : ...

1 : ...

... select bit

0 : ...

1 : ...

The value is “0” at reading.

0 : ...

1 : ...

Fix this bit to “0.”

7 to 5 Not implemented.

Bit

Bit name

This bit is ignored in ... mode.

Functions

At reset

... flag

Undefined

Blank : Set to “0” or “1” according to the usage.

: Set to “0” at writing.

: Set to “1” at writing.

: Ignored depending on the mode or state. It may be “0” or “1.”

: Not implemented.

: “0” immediately after reset.

: “1” immediately after reset.

Undefined : Undefined immediately after reset.

: It is possible to read the bit state at reading. The written value becomes valid.

: It is possible to read the bit state at reading. The written value becomes

invalid. Accordingly, the written value may be “0” or “1.”

: The written value becomes valid. It is impossible to read the bit state. The

value is undefined at reading. However, when [“0” at reading] is indicated in

the “Function” or “Note” column, the bit is always “0” at reading.(See to V4

above.)

—

: It is impossible to read the bit state. The value is undefined at reading.

However, when [“0” at reading] is indicated in the “Function” or “Note” column,

the bit is always “0” at reading.(See to V4 above.)

The written value becomes invalid. Accordingly, the written value may be “0”

or “1.”

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