7733 datasheet(562/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21-14

Appendix 3. Control registers

UART0, UART1 transmit/receive mode register

Bit

Sleep selection bit

(Valid in the UART mode.) (Note)

Parity enable bit

(Valid in the UART mode.) (Note)

Odd/Even parity selection bit

(Valid in the UART mode when

the parity enable bit = “1.”)

(Note)

Stop bit length selection bit

(Valid in the UART mode.)

(Note)

Internal/External clock selection

bit

Serial I/O mode selection bits

Bit name

At reset

Functions

0 0 0: Serial I/O is disabled.

(P8 functions as a

programmable I/O port.)

0 0 1: Clock synchronous serial I/O

mode

0 1 0: Do not select.

0 1 1: Do not select.

1 0 0: UART mode

(Transfer data length = 7 bits)

1 0 1: UART mode

(Transfer data length = 8 bits)

1 1 0: UART mode

(Transfer data length = 9 bits)

1 1 1: Do not select.

UART0 transmit/receive mode register (address 3016)

UART1 transmit/receive mode register (address 3816)

Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be “0” or “1.”)

Fix bit 7 to “0.”

b2 b1 b0

0: Odd parity

1: Even parity

0: Parity is disabled.

1: Parity is enabled.

0: The sleep mode is terminated. (Ignored.)

1: The sleep mode is selected.

0: Internal clock

1: External clock

0: One stop bit

1: Two stop bits

UARTi baud rate register (BRGi)

UART0 baud rate register (address 3116)

UART1 baud rate register (address 3916)

UART2 baud rate register (address 6516)

Functions

Bit

At reset

7 to 0

Values 0016 to FF16 can be set.

Assuming that the set value = n, BRGi

divides the count source frequency by (n + 1).

Un-

defined

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