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7733 Scheda tecnica(PDF) 563 Page - Renesas Technology Corp

Il numero della parte 7733
Spiegazioni elettronici  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7733 Scheda tecnica(HTML) 563 Page - Renesas Technology Corp

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APPENDIX
7733 Group User’s Manual
21-15
Appendix 3. Control registers
UARTi transmission buffer register
b7
b0
(b15)
(b8)
b7
b0
UART0 transmission buffer register (addresses 3316, 3216)
UART1 transmission buffer register (addresses 3B16, 3A16)
UART2 transmission buffer register (addresses 6716, 6616)
Bit
Not implemented.
The transmit data is set.
At reset
Un-
defined
RW
Functions
8 to 0
15 to 9
Un-
defined
WO
—
UART0, UART1 transmit/receive control register 0
0: At the falling edge of the transfer
clock, transmit data is output; at
the rising edge of the transfer
clock, receive data is input.
When not in transferring, pin
CLKi’s level is “H.”
1: At the rising edge of the transfer
clock, transmit data is output; at
the falling edge of the transfer
clock, receive data is input.
When not in transferring, pin
CLKi’s level is “L.”
0: The CTS/RTS function is enabled.
1: The CTS/RTS function is disabled.
(P80 and P84 function as
programmable I/O ports.)
(Valid when the CTS/RTS enable
bit is “0.”)
2
CTS
/RTS function selection bit
Bit
1
0
BRG count source selection bits
Bit name
At reset
0: Data is present in the transmission
register. (Transmission is in progress.)
1: No data is present in the transmission
register. (Transmission is completed.)
RW
Functions
b7
b6
b5
b4
b3
b2
b1
b0
0 0: Clock f2
0 1: Clock f16
1 0: Clock f64
1 1: Clock f512
UART0 transmit/receive control register 0 (address 3416)
UART1 transmit/receive control register 0 (address 3C16)
b1 b0
0: The CTS function is selected.
1: The RTS function is selected.
4
CTS
/RTS enable bit
3
Transmission register empty flag
0
1
0
0
0
Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”
Note: Fix bits 6 and 7 to “0” in the UART mode.
5
Data output selection bit
0: Pin TxDi is set for CMOS output.
1: Pin TxDi is set for N-channel open-
drain output.
0
6
0
7
0: LSB (Least Significant Bit) first
1: MSB (Most Significant Bit) first
0
CLK polarity selection bit
(This bit is used in the clock
synchronous serial I/O mode.)
(Note)
Transfer format selection bit
(This bit is used in the clock
synchronous serial I/O mode.)
(Note)
RW
RW
RW
RO
RW
RW
RW
RW



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