7733 datasheet(569/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21-21

Appendix 3. Control registers

Timer A2 mode register (address 5816)

Timer A3 mode register (address 5916)

Timer A4 mode register (address 5A16)

Bit

Up-down switching factor

selection bit

Operating mode selection

bits

Bit name

Count type selection bit

Must be fixed to “0” in the event counter mode.

Note: This bit is valid only for the timer A3 mode register.

For the timer A2 and A4 mode registers, this bit is ignored. (It may be “0” or “1.”)

Two-phase pulse signal

processing type selection

bit (Note)

Functions

0 1: Event counter mode

b1 b0

0: Contents of the up-down flag

1: A signal which is input to pin TA2OUT,

TA3OUT, or TA4OUT

At reset

Pulse output function

selection bit

0: No pulse is output. (Pin TA2OUT, TA3OUT, or

TA4OUT functions as a programmable I/O

port.)

1: Pulse is output. (Pin TA2OUT, TA3OUT, or

TA4OUT functions as a pulse output pin.)

Count polarity selection bit

0: Counting is performed at the falling edge of

the external signal.

1: Counting is performed at the rising edge of

the external signal.

0: Reload count type

1: Free-run count type

0: Normal processing

1: Quadruple processing

(b15)

(b8)

Functions

Bit

At reset

15 to 0 Values 000016 to FFFF16 can be set.

Assuming that the set value = n, counter

divides the count source frequency by (n + 1)

in down-counting, or by (FFFF16 – n + 1) in

up-counting.

At reading this register, the counter value is

read out.

Undefined

Timer A2 register (addresses 4B16, 4A16)

Timer A3 register (addresses 4D16, 4C16)

Timer A4 register (addresses 4F16, 4E16)

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