7733 datasheet(254/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–51

8.4 Clock asynchronous serial I/O (UART) mode

Fig. 8.4.4 How to write data after transmission is started

[When not using interrupts]

[When using interrupts]

A UARTi transmission interrupt request occurs

when the UARTi transmission buffer register

becomes empty.

UARTi transmission interrupt

UART0 transmission buffer register (addresses 33 16, 3216)

UART1 transmission buffer register (addresses 3B 16, 3A16)

UART2 transmission buffer register (addresses 67 16, 6616)

b15

Writing of the next transmit data

Transmit data is set here.

g This diagram indicates bits and registers

required for processing.

Refer to Figures 8.4.6, 8.4.7 and 8.4.8

for details about the change of flag

status and the occurrence timing of an

interrupt request.

UART0 transmit/receive control register 1 (address 35 16)

UART1 transmit/receive control register 1 (address 3D 16)

UART2 transmit/receive control register 1 (address 69 16)

Transmission buffer empty flag

0: Data is present in the transmission buffer register.

1: No data is present in the transmission buffer register.

(Next transmit data can be written.)

Checking the status of the UARTi transmission buffer register

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