AM1808AZCED3 datasheet(129/264 Pages) TI

129 / 264 page

AM1808

www.ti.com

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-44. SATA PCB Stackup Specifications (continued)

PARAMETER

MIN

TYP

MAX

UNIT

Number of layers between SATA routing region and reference ground plane

PCB Routing Feature Size

Mils

PCB Trace Width w

Mils

PCB BGA escape via pad size

Mils

PCB BGA escape via hole size

Mils

Device BGA pad size (1)

(1)

Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.

6.14.2.4 Routing Specifications

The SATA data signal traces are edge-coupled and must be routed to achieve exactly 100 Ohms

differential impedance. This is impacted by trace width, trace spacing, distance between planes, and

dielectric material. Verify with a proper PCB manufacturing tool that the trace geometry for both data

signal pairs results in exactly 100 ohms differential impedance traces. Table 6-45 shows the routing

specifications for the data and REFCLK signals .

Table 6-45. SATA Routing Specifications

PARAMETER

MIN

TYP

MAX

UNIT

Device to SATA header trace length

7000

Mils

REFCLK trace length from oscillator to Device

2000

Mils

Number of stubs allowed on SATA traces

Stubs

TX/RX pair differential impedance

100

Ohms

Number of vias on each SATA trace

Vias (1)

2*DS

SATA differential pair to any other trace spacing

(2)

(1)

Vias must be used in pairs with their distance minimized.

(2)

DS is the differential spacing of the SATA traces.

6.14.2.5 Coupling Capacitors

AC coupling capacitors are required on the receive data pair as well as the REFCLK pair. Table 6-46

shows the requirements for these capacitors.

Table 6-46. SATA Bypass and Coupling Capacitors Requirements

PARAMETER

MIN

TYP

MAX

UNIT

SATA AC coupling capacitor value

0.3

µF

10 Mils (1)

SATA AC coupling capacitor package size

0603

(2)

(1)

LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor.

(2)

The physical size of the capacitor should be as small as possible.

6.14.2.6 SATA Interface Clock Source requirements

A high-quality, low-jitter differential clock source is required for the SATA PHY. The SATA interface

requires

LVDS

differential

clock

source

provided

signals

SATA_REFCLKP

and

SATA_REFCLKN. The clock source should be placed physically as close to the processor as possible.

Table 6-47 shows the requirements for the clock source.

Peripheral Information and Electrical Specifications

129

Submit Documentation Feedback

Product Folder Link(s): AM1808

AM1808AZCED3 Scheda tecnica(PDF) 129 Page - Texas Instruments

AM1808AZCED3 Scheda tecnica(HTML) 129 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL