AM1808AZCED3 datasheet(131/264 Pages) TI

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ReceiveLogic

C lo ck /F ra m e G e n e ra to r

StateMachine

ClockCheckand

Serializer0

Serializer1

Serializery

GIO

Control

DITRAM

384C

384U

Optional

Tra n s m it

F o rm a tte r

Receive

F o rm a tte r

Tra n s m it L o g ic

C lo ck /F ra m e G e n e ra to r

StateMachine

McASP

Peripheral

Configuration

Bus

McASP

DMA Bus

(Dedicated)

AHCLKRx

ACLKRx

AFSRx

AMUTEINx

AMUTEx

AFSXx

ACLKXx

AHCLKXx

AXRx[0]

AXRx[1]

AXRx[y]

Pins

Function

ReceiveMasterClock

ReceiveBitClock

R e c e iv e L e ft/R ig h t C lo ck o r F ra m e S y n c

Tra n s m it M a s te r C lo ck

Tra n s m it B it C lo ck

Tra n s m it L e ft/R ig h t C lo ck o r F ra m e S y n c

Tra n s m it/R e c e iv e S e ria l D a ta P in

ErrorDetection

TheMcASP DOESNOThavea

dedicated AMUTEINpin.

AM1808

www.ti.com

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

6.15 Multichannel Audio Serial Port (McASP)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

•

Flexible clock and frame sync generation logic and on-chip dividers

•

Up to sixteen transmit or receive data pins and serializers

•

Large number of serial data format options, including:

–

TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)

–

Time slots of 8,12,16, 20, 24, 28, and 32 bits

–

First bit delay 0, 1, or 2 clocks

–

MSB or LSB first bit order

–

Left- or right-aligned data words within time slots

•

DIT Mode with 384-bit Channel Status and 384-bit User Data registers

•

Extensive error checking and mute generation logic

•

All unused pins GPIO-capable

•

Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it

more tolerant to DMA latency.

•

Dynamic Adjustment of Clock Dividers

–

Clock Divider Value may be changed without resetting the McASP

Figure 6-29. McASP Block Diagram

Peripheral Information and Electrical Specifications

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