AM1808AZCED3 datasheet(141/264 Pages) TI

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AM1808

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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

6.16.2 McBSP Electrical Data/Timing

The following assume testing over recommended operating conditions.

6.16.2.1

Multichannel Buffered Serial Port (McBSP) Timing

Table 6-57. Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V](1) (see Figure 6-32)

1.3V, 1.2V

1.1V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

2P or 20(2) (3)

2P or 25(2) (3)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

P - 1(4)

CLKR int

15.5

Setup time, external FSR high before CLKR

tsu(FRH-CKRL)

low

CLKR ext

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

CLKR int

15.5

tsu(DRV-CKRL) Setup time, DR valid before CLKR low

CLKR ext

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

CLKX int

15.5

tsu(FXH-CKXL) Setup time, external FSX high before CLKX low

CLKX ext

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(3)

Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(4)

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Peripheral Information and Electrical Specifications

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