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WM8961 Scheda tecnica(PDF) 42 Page - Wolfson Microelectronics plc |
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WM8961 Scheda tecnica(HTML) 42 Page - Wolfson Microelectronics plc |
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42 / 116 page  WM8961 Pre-Production w PP, August 2009, Rev 3.1 42 + - AGND + + VPOS VNEG + - AGND + + VPOS VNEG Left Headphone Analog Output Stage Right Headphone Analog Output Stage DC Servo R61, DCS_ENA_CHAN_HPL R61, DCS_ENA_CHAN_HPR HPL_VOL[2:0] HPR_VOL[2:0] HP_L HP_R - + Left Headphone PGA - + Right Headphone PGA R2, LOUT1VOL[6:0] R2, LOUT1VOL[6:0] R26, LOUT1_PGA R3, ROUT1VOL[6:0] R3, ROUT1VOL[6:0] R26, ROUT1_PGA -73dB to +6dB, in steps of 1dB -73dB to +6dB, in steps of 1dB LDAC RDAC Figure 18 Headphone Analogue Output Stage HEADPHONE VOLUME PGA The signal volume on HP_L and HP_R can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting below 0101111 (minimum) mutes the output driver. The LOUT1VOL and ROUT1VOL register writes should only be carried out after the charge pump has been enabled, see the “Charge Pump” section for details. A zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gain updates. If zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R23 (17h). The timeout period is set by CLK_TO_DIV[1:0]. The volume control PGAs are enabled using LOUT1_PGA and ROUT1_PGA. |
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